Recently, the time interval between data signals input to fast response semiconductor devices has become shorter. A number of semiconductor devices include a plurality of input circuits which accept two or four data via an external input terminal in response to one clock signal. Such a semiconductor device may include memories having a fast data transfer capability such as Double Data Rate Synchronous DRAM (DDRSDRAM) and Quad Data Rate (QDR) SRAM, the time interval between data which are input to input circuits for such a semiconductor device is for example 312.5 ps when the device is operated at a frequency of for example, 3.2 Ghz, so that a kick back which is caused when an input circuit senses data at an edge of a clock signal may give an adverse influence upon data sense at next clock edge.
An effect of kick back in the input circuits will now be described. FIG. 7 is a circuit diagram showing an exemplary configuration of a first stage circuit of a typical input circuit (hereinafter simply referred to as “input circuit”) which is used in fast memories and the like. A transistor Q100 (generally referred to as BVDS transistor) which is an electrostatic discharge protecting element is directly connected to a pad PAD to which data signals are input. The pad PAD is connected to a transistor Q101 which is an electrostatic protecting element via a resistor element R100 and then connected to the gate of transistor Q102 at the first stage of the input circuit 100. The size of the transistor Q100 is 50 times of that of the transistor Q101, so that its electrostatic discharge protecting capability is enhanced. The size of the transistor Q101 is approximately equal to that of the transistors used in the input circuit 100. A large bipolar diode may be connected in lieu of the transistor Q100. An example of such an input protective circuit is disclosed in, for example, Patent Document No. 1 and the like.
In FIG. 7, transistors Q102 and Q103 constitute a differential amplifier of the first stage of the input circuit 100, which is operative when the clock CK becomes the high level. Output signals OUT1 and OUT2 which are in an opposite phase are output via flip-flops which are formed of transistors Q109 and Q110, Q111 and Q112, which are loads of the differential amplifier depending upon whether the potential at the gate of the transistor Q102 is higher or lower than that of a reference signal applied to the gate of transistor Q103. On the other hand, when the clock CK is in the low level, transistor Q104 is turned off, so that transistors Q102 and Q103 are not operative, while transistors Q107 and Q108 are turned on, so that output signals OUT1, OUT2 are in the high level.
Since the clock CK is in the low level, transistor Q104 is turned off, all of the inner contacts of the input circuit are precharged to a voltage of about VDD. When clock CK becomes high level, differential amplification begins, so that a result is ultimately latched at the flip-flop which constitutes load. As a result, all of the sources and drains of the transistors of the differential amplifier become GND level and an opposing electrode of the gate of transistor Q102 becomes GND potential so that the potential at the gate is slightly lowered due to charge of the gate capacitance. Conversely, when the opposing electrode is reset and in the precharged state, it is charged to about the level of VDD and the charge on the gate is discharged to elevate the potential at the gate.
When the first input stage of the input circuit 100 is controlled by clock CK as mentioned above, the potential at the stage of transistor Q102 will change whenever the level of the clock CK changes. This phenomenon is called “kick back”. If an other circuit is connected to the gate of transistor Q102, this kick back will give an influence upon the other circuit.
A semiconductor device in which a time lag due to the presence of an input protective resistor and the gate capacity of a transistor at a first stage is made shorter to make response speed faster is disclosed in Patent Document 2. This semiconductor device is configured so that one external input signal path is divided into plural parts, each of is provided with an which input protective circuit.
A semiconductor integrated circuit in which its input circuit of MOS integrated circuit is operated at a high speed without decreasing the resistance of the input protective resistor is disclosed in Patent Document No. 3. In this semiconductor integrated circuit, a plurality of input portions each comprising an input protective circuit and input circuit are connected in a parallel manner between an input terminal and inner logical circuits. This makes it possible to make the period for which the output voltage of the input circuit changes shorter by increasing the driving power of the input circuit even if the minimum value of the resistance of the input protective resistor is determined.
[Patent Document 1] Japanese Patent Kokai Publication No. JP-A-5-335493
[Patent Document 2] Japanese Patent Kokai Publication No. JP-A-62-154665
[Patent Document 3] Japanese Patent Kokai Publication No. JP-A-7-326713